A Unifying Approach for Weighted and Diminished-1 Modulo Addition
نویسندگان
چکیده
In this paper, it is shown that every architecture proposed for modulo addition of operands that follow the diminished-1 representation can also be used in the design of modulo adders for operands that follow the weighted representation. This is achieved by the addition of a constant-time operator composed of a simplified carry-save adder stage. The experimental results indicate that many architectures already proposed for the diminished-1 case, lead to very efficient adders for weighted operands, under this unifying approach.
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